The invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body with a bipolar transistor including a base, an emitter and a collector, said base being formed by providing the semiconductor body with a doped semiconducting layer which locally borders on a monocrystalline part of the semiconductor body where it forms a first semiconductor region which is monocrystalline and constitutes the base of the transistor, and which semiconductive layer borders, outside said base, on a non-monocrystalline part of the semiconductor body where it forms a second semiconductor region which is not monocrystalline and which constitutes a connection region of the base, the non-monocrystalline part of the semiconductor body being obtained by covering the semiconductor body with a mask and replacing, on either side thereof, a part of the semiconductor body by an electrically insulating region, and by providing the electrically insulating region with a polycrystalline semiconducting layer before the provision of the semiconducting layer.
Such a method is known from European patent application, filed by the current applicant (PHN 17.066) under application no. 98202894.6 on Aug. 31, 1998. In said document, a description is given of a method for the manufacture of a so-called differential bipolar transistor. Such a transistor is obtained by providing a semiconducting layer on a crystalline and a non-crystalline part of the semiconductor body, which forms at said locations, respectively, a crystalline semiconductor region, the base of the transistor, and a non-crystalline semiconductor region, a connecting region of the base. The crystalline part of the semiconductor body forms the collector, and in the semiconducting layer the emitter is formed at the location of the base. The non-monocrystalline part of the semiconductor body is formed by an electrically insulating region which surrounds the collector and on which a polycrystalline semiconducting layer is situated which serves as the host layer during the provision of the semiconducting layer. The electrically insulating region is formed by a LOCOS (=Local Oxidation Of Silicon) oxide on which a polycrystalline layer is provided in which an aperture is formed at the location of the collector by means of photolithography and etching.
A drawback of the known method is that it is relatively laborious, partly because a photolithographic step followed by an etch step is necessary to form an aperture in the polycrystalline layer above the collector.